Global parity symbol for interleaved reed-solomon coded data

ABSTRACT

A circuit and method includes a global parity symbol in a multi-way interleaved Reed-Solomon code implementation to enhance error-detection capability of the Reed-Solomon code. In one embodiment, the global parity symbol is computed over both the data symbols and the check symbols of the Reed-Solomon code, thereby providing data detection capability for errors occurring in the check symbols.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to electronic circuits for ensuring dataintegrity in data storage or data communication applications; inparticular, this invention relates to minimizing the probability ofmiscorrection in applying error correction and error detection codes todata storage and data communication applications.

2. Discussion of the Related Art

Error correction and error detection codes have been used extensively indata communication and data storage applications. In a datacommunication application, data is encoded prior to transmission, anddecoded at the receiver. In a data storage application, data is encodedwhen stored in a storage device, e.g. a disk drive, and decoded whenretrieved from the storage device. For the present discussion, it isunnecessary to distinguish between these applications. Hence, althoughthe remainder of this description describes a data storage-retrievalsystem, the principles discussed herein are equally applicable to a datacommunication application.

In a typical application of error detection and correction codes, datasymbols are stored in blocks, which each include a selected number ofspecial symbols, called check symbols. A symbol may consist of a singlebit or multiple bits. The check symbols in each block representredundant information concerning the data stored in the block. Whendecoding the blocked data, the check symbols are used to detect both thepresence and the locations of errors and, in some instances, correctthese errors. The theory and applications of error correction codes aredescribed extensively in the literature. For example, the texts (i)"Error-Correcting Codes", Second Edition, by W. Wesley Peterson and E.J. Weldon, published by the MIT Press, Cambridge, Mass. (1972), and (ii)"Practical Error Correction Design for Engineers", revised secondedition, by N. Glover and T. Dudley, Cirrus Logic, Colorado, publisher(1991), are well-known to those skilled in the art.

In a typical application of error correction codes, the input data isdivided into fixed-length blocks ("code words"). Each code word consistsof n symbols, of which a fixed number k are data symbols, and theremaining (n-k) symbols are check symbols. (For convenience, in thisdescription, such a code is referred to as an (n, k) code). As mentionedabove, the check symbols represent redundant information about the codeword and can be used to provide error correction and detectioncapabilities. Conceptually, each data or check symbol of such a codeword represents a coefficient of a polynomial of order (n-1). In theerror correcting and detecting codes of this application, the checksymbols are the coefficients of the remainder polynomial generated bydividing the order (n-1) polynomial by an order (n-k) "generator"polynomial over a Galois field¹. For an order (n-1) polynomial dividedby an order (n-k) polynomial, the remainder polynomial is of order(n-k-1). Typically, in a data storage application, both the data symbolsand the check symbols are stored.

During decoding, both data symbols and check symbols are read from thestorage medium, and one or more "syndromes" are computed from the codeword (i.e. the data and the check symbols) retrieved. A syndrome is acharacteristic value computed from a remainder polynomial, which isobtained by dividing the code word retrieved by the generatorpolynomial. Ideally, if no error is encountered during the decodingprocess, all computed syndromes are zero.² A non-zero syndrome indicatesthat one or more errors exist in the code word. Depending on the natureof the generator polynomial, the encountered error may or may not becorrectable. If the generator polynomial can be factorized, a syndromecomputed from the remainder polynomial obtained by dividing theretrieved code word by one of the factors of the generator polynomial iscalled a "partial syndrome".

A useful measure for quantifying the difference between two binary wordsis the "Hamming distance", which is defined as the number of bitpositions at which the two words differ. For example, the 4-bit words`0000` and `0010` have between them a Hamming distance of one sincethese words differ only at the second least significant bit. In thedesign of error correction codes or error detection codes, a measure"minimum distance" can be defined. The minimum distance is the minimumHamming distance between valid code words. In such an error correctionor detection code, if the valid code word and the retrieved code wordhave a Hamming distance between them which is less than the minimumdistance, the probability is high that the retrieved code word resultsfrom errors occurring in the valid code word at the bit positionsdefining the Hamming distance between these words. Thus, in errorcorrection codes, the decoder can resolve, with minimum risk ofmiscorrecting the retrieved code word, in favor of the valid code wordhaving the smallest Hamming distance from the retrieved code word³. Ofcourse, if the minimum distance is an even integer, ambiguity for errorcorrection exists when a retrieved code word is the same Hammingdistance from two or more valid code words. For an error correcting codewith a minimum distance d, the numbers of errors which can be correctedand detected are ##EQU1## respectively. The concepts of the Hammingdistance and the minimum distance can be extended to multi-bit symbols.In such an extension, the Hamming distance and the minimum distance areeach expressed in symbol units. For example, if an error correction codeusing multi-bit symbols, the Hamming distance is defined as the numberof symbol positions at which two code words differ. In such an errorcorrection code, two code words differ by a distance of one, if theydiffer at one symbol position, regardless of the number of bit positionsthese code words differ within the corresponding symbols at that symbolposition.

One goal in designing error correction and error detection codes is theselection of an appropriate minimum distance. In general, the minimumdistance of an error correction code can be increased by increasing thenumber of check symbols in a code word. At the same time, however,increasing the number of check symbols in a code word increases both thecomplexity of the necessary decoding logic and the overhead cost (interms of decoding time and storage space) associated with the additionalcheck symbols. The capability of an error correction or detection codeis sometimes characterized by the size of the maximum error burst thecode can correct or detect. For example, a convenient capability measureis the "single error burst correction" capability, which characterizesthe code by the maximum length of consecutive error bits the code cancorrect, as measured from the first error bit to the last error bit, ifa single burst of error occurs within a code word. Another example of acapability measure would be the "double error burst detection"capability, which characterizes the error correction or error detectioncode by the maximum length of each error burst the error correction codecan detect, given that two or less bursts of error occur within a codeword.

A well-known class of error correcting codes is the Reed-Solomon codes,which are characterized by the generator polynomial G(X), given by:

    G(X)=(X+α.sup.j)(X+α.sup.j+1)(X+α.sup.j+2) . . . (X+α.sup.j+i-1)(X+α.sup.j+i)

where α is a primitive element of GF(2^(m)) and, i and j are integers.

Because errors often occur in bursts, a technique, called"interleaving", is often used to spread the consecutive error bits orsymbols into different "interleaves", which can each be correctedindividually. Interleaving is achieved by creating a code word of lengthnw from w code words of length n. In one method for forming the new codeword, the first w symbols of the new code word are provided by the firstsymbols of the w code words taken in a predetermined order. In the samepredetermined order, the next symbol in each of the w code words isselected to be the next symbol in the new code word. This process isrepeated until the last symbol of each of the w code words is selectedin the predetermined order into the new code word. Another method tocreate a w-way interleaved code is to replace a generator polynomialG(X) of an (n, k) code by the generator polynomial G(X^(w)). Thistechnique is applicable, for example to the Reed-Solomon codes mentionedabove. Using this new generator polynomial G(X^(w)), the resulting (nw,kw) code has the error correcting and detecting capability of theoriginal (n, k) code in each of the w interleaves so formed.

Another approach used in the prior art for error detection is the use ofthe cyclic redundancy check (CRC) symbols. Under this approach, a CRCchecksum, which is the value of a polynomial function applied to theinput data, is computed. This CRC checksum is transmitted or stored withthe data and is recomputed at the receiver or when retrieved. If noerror is encountered, the computed CRC checksum matches the retrieved orreceived CRC checksum. Otherwise, one or more errors exist in the dataor the retrieved CRC checksum. Unlike error correction codes, the CRCchecksum does not pin-point where the error or errors occur, and thusdoes not provide the capability for correcting errors.

In a practical implementation, the full error correction capability ofan error correction code is often not fully exploited because thecomplexity of logic circuits required for error location and errorcorrection can become prohibitive for a relatively small minimumdistance. It is, however, desirable to exploit the full capability oferror detection, even though the full capability of error correction isnot exploited. Indeed, in some applications, the consequence of amiscorrection is extremely undesirable. In those applications, an erroris merely flagged, so that some other error recovery procedures may takeover. For example, in a disk drive application, during data read, noisemay cause a transient error in the magnetic head mechanism. Such anerror is best handled by re-reading the sector from which the erroroccurred, rather than by attempting to correct the faulty data. In suchan application, the additional cost of exploiting the full capability ofthe error correction code may not be economically justified.

SUMMARY OF THE INVENTION

In accordance with the present invention, in an interleaved Reed-Solomonerror correcting code, a method is provided for increasing the minimumdistance in each interleave by including only a single global paritysymbol. The method of the present invention includes the steps of: (a)receiving a plurality of data symbols; (b) computing, in eachinterleave, a code word including the data symbols and a plurality ofcheck symbols, the check symbols being generated by a generatorpolynomial given by:

    G(X)=(X+α.sup.j)(X+α.sup.j+1)(X+α.sup.j+2) . . . (X+αj+i-1)(X+α.sup.j+i)

where α is a primitive element of GF(2^(m)) and, i and j are integers;and (c) providing a global parity symbol GP associated with a syndromeS_(GP) given by one of: ##EQU3## where γ₀, γ₁, . . . , γ_(w-1) arenon-zero elements of a galois field GF(2^(m)) , andS.sub.(i+j+1)w.sbsb.0 and S.sub.(j-m)w.sbsb.0 are, respectively, thepartial syndromes corresponding to (X+α^(i+j+1)) and (X+α^(j-1)) forinterleave w₀.

In accordance with one aspect of the present invention, the methodprovides check symbols of a Reed-Solomon code using a single generatorpolynomial:

    G.sub.w (X)=(X.sup.w +α.sup.j)(X.sup.w +α.sup.j+1) . . . (X.sup.w +α.sup.j+i-1)(X.sup.w +α.sup.j+i)

In accordance with another aspect of the present invention, when thenumber w of interleaves divides (j+i+1), the global parity symbol GP canbe computed over all interleaves using a single second generatorfunction ##EQU4## Alternatively, when the number w of interleavesdivides (j-1), the global parity symbol GP can be computed over allinterleaves using a single second generator function ##EQU5## Bycomputing the global parity symbol GP over all interleaves using asingle second generator function, the amount of hardware used togenerate global parity symbol GP is greatly reduced.

In one embodiment, the global parity symbol GP is computed as part ofthe Reed-Solomon error correction code word. For example, such aReed-Solomon error correction code can be generator by the generatorpolynomial: ##EQU6##

When the global parity symbol GP is computed as part of the Reed-Solomoncode word, if an error occurs with in the parity symbol GP, such errorcan be corrected using the error correction capability of theReed-Solomon code.

The error correcting code of the present invention can be decoded bycomputing partial syndromes S_(j), S_(j+1), S_(j+2), . . . , S_(j+i), ofthe generator function and the syndrome S_(GP).

In one embodiment, the decoding circuit limits error correction to asingle error burst of less than a predetermined number of symbols. Inthat embodiment, the Reed-Solomon error correcting code is 3-wayinterleaved. In accordance with the present invention, the Reed-Solomonerror correcting code of that embodiment, estimates the syndrome S_(GP)using the relation:

    S.sub.GP =S.sub.3 (α)=S.sub.32 α.sup.2 +S.sub.31 α+S.sub.30

In another embodiment, a 3-way interleaved Reed-Solomon error correctingcode generates a global parity symbol GP using a polynomial (X+α^(v)),where v is an integer. In that embodiment, the syndrome S_(GP) isestimated using the relation:

    S.sub.GP =S.sub.32 α.sup.2v +S.sub.31 α.sup.v +S.sub.30

One advantage of the present invention over the prior art is that, in aninterleaved implementation, the Hamming distance for each interleave isincreased by one. In other words, the present invention increases thenumber of errors detectable in each interleave by one. The presentinvention achieves this increase in Hamming distance in each interleaveby including a single global check symbol, rather than by including acheck symbol in each interleave, as is required in the prior art.

The present invention is better understood upon consideration of thedetailed description below and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an organization of a Reed-Solomon code used in oneembodiment of the present invention.

FIG. 2 is a feedback shift register circuit 200 which is used forgenerating check symbols and which receives one data symbol per clockperiod.

FIG. 3 is a feedback shift register circuit 300 for generating checksymbols and which receives two data symbols per clock period, inaccordance with one embodiment of the present invention.

FIG. 4a, 4b and 4c show respectively partial syndrome circuits 400, 430and 433 for computing the coefficients of partial syndromes S₀, S₁, andS₂ respectively.

FIG. 5 shows schematically a decoder 500 in accordance with the presentinvention.

FIG. 6 shows a burst limiter circuit 500 providing a 2-byte errorpattern ERRPAT from the error patterns in each interleave and the errorpattern corresponding to a global parity error.

FIG. 7 shows a schematic circuit for computing a global parity syndromeS_(GP2) based on an estimated global parity syndrome ES_(GP) and acomputed global parity syndrome S_(GP).

FIG. 8, also referred to as Table 1, shows the 16 elements of the Galoisfield GF(2⁴) used in an embodiment of the present invention.

FIG. 9, also referred to as Table 2, shows the derivation of the logicequations for check symbol generation circuit 200 illustrated in FIG. 2.

FIG. 10, also referred to as Table 3, shows the logic equation for eachof the bits in the results of multiplying a 4-bit data symbol β toconstants α, α², and α³, α¹⁰, and α¹¹ respectively within the Galoisfield GF(2⁴) defined in Table 1.

FIG. 11, also referred to as Table 4, shows the logic equations for thenext coefficients of syndromes S_(i) (i=0, 1, and 2) in circuits 400,430 and 460, as expressed in terms of input values d_(h) and d_(l), andthe previous values r_(ij) (i,j=0, 1, and 2) of syndromes S_(i).

FIGS. 12A, 12B and 12C, also respectively referred to as Tables 5a, 5band 5c, provide the physical locations of errors occurring in therespective one of interleaves 0, 1, and 2, in the present embodiment.

FIG. 13, also referred to as Table 6, shows the various error conditionsin an interleave recognized by the present embodiment.

FIG. 14, also referred to as Table 7, shows the multiplicative inversesof the elements in the Galois field GF(2⁴) defined in Table 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is illustrated by an implementation using 4-bitsymbols in a Galois field GF(2⁴), which is defined by the followingprimitive polynomial over Galois field GF(2):

    f(x)=x.sup.4 +x+1

where x denotes a single bit.

Table 1 shows a zero and the 15 non-zero elements α^(i) of the Galoisfield GF(2⁴) so defined. In such a Galois field, the element α is knownas a "primitive" element. Note that the Galois field GF(2⁴) generated bythe above primitive polynomial is only one of the possible extended4-bit Galois fields derivable from the Galois field GF(2), i.e. there isat least one other primitive polynomial that generates another extendedGalois field GF(2⁴) different from the one shown in FIG. 1. However, inthe remainder of this detailed description, any reference below to aGF(2⁴) Galois field is understood to refer to the GF(2⁴) Galois fieldtabulated in Table 1.

The present invention provides a global parity ("GP") symbol inconjunction with a w-way interleaved Reed-Solomon code. According to thepresent invention, the GP symbol is computed from a set of paritysymbols which, in turn, are each computed from data and check symbols ina single interleave. In the present invention, the GP symbol istransmitted or stored with the Reed-Solomon code, either as part of theReed-Solomon code or apart from the Reed-Solomon code. The paritysymbols from which the GP symbol is calculated need not be transmittedor stored.

Conventionally, one example of a Reed-Solomon code having a minimumdistance of 5 has a generator polynomial g(X), given by:

    g(X)=(X+1)(X+α)(X+α.sup.2)(X+α.sup.3)

where X denotes a symbol.

As discussed above, based on the above generator function, a three-wayinterleave Reed-Solomon code having the same distance of 5 in eachinterleave can be obtained using a generator polynomial g'(X), which isgiven by:

    g'(X)=(X.sup.3 +1)(X.sup.3 +α)(X.sup.3 +α.sup.2)(X.sup.3 +α.sup.3)

Polynomial g'(X) would have a distance of 5 in each interleave, i.e. amaximum of two errors can be corrected and additional 3 errors can bedetected in each interleave. Clearly, twelve check symbols are requiredunder this approach to achieve the minimum distance of 5 in eachinterleave.

As will be demonstrated below, the present invention provides a singleglobal parity symbol GP, in lieu of extra w check symbols of a w-wayinterleaved Reed-Solomon code, without reducing the minimum Hammingdistance of each interleave in the resulting code word. Thus, forexample, under the present embodiment, the total number of check symbolsrequired to be stored or transmitted, including the GP symbol, would bereduced from twelve to ten, without affecting the minimum distance of 5in each interleave. Equivalently, by incorporating only a single globalparity symbol GP, rather than the number of check symbols equalling thenumber of interleaves, the present invention increases an interleavedReed-Solomon code's Hamming distance in each interleave by one.

In general, for a w-way interleave implementation, in which the codeword in each interleave is generated by the generator polynomial:

    G(X)=(X+α.sup.j)(X+α.sup.j+1)(X+α.sup.j+2) . . . (X+α.sup.j+i-1)(X+α.sup.j+i)

where α is a primitive element of GF(2^(m)) and, i and j are integers,the global syndrome S_(GP) can be provided by either: ##EQU7## where γ₀,γ₁, . . . , γ_(w-1) are non-zero elements of GF(2^(m)), andS.sub.(i+j+1) w.sbsb.0 and S.sub.(j-1) w.sbsb.0 are, respectively, thepartial syndromes for interleave w₀ corresponding to (X+α^(i+j+1)) and(X+α^(j-1)). Further, the w-way interleaved code word can also begenerated by a single generator polynomial:

    G.sub.w (X)=(X.sup.w +α.sup.j)(X.sup.w +α.sup.j+1) . . . (X.sup.w +α.sup.j+i-1)(X.sup.w +α.sup.j+i)

In this instance, when the number of interleaves (i.e. w) divides either(j+i+1) or (j-1), one possible global parity syndrome S_(GP) can becomputed over all interleaves using a single second generator function##EQU8## rather than a sum of individual syndromes from each interleave.Calculating S_(GP) in this manner is possible because, according toremainder theorem, when w divides (i+j+1), then ##EQU9## is a factor of(X^(w) +α^(i+j+1)). Likewise, if w divides (j-1), then ##EQU10## is afactor of (X^(w) +α^(j-1)).

The global parity symbol GP may be computed as part of the code word, oroutside of the code word. If the global parity symbol GP is computed aspart of the code word, error occurring in the GP symbol can be correctedor detected, as in Reed-Solomon code word.

A three-way interleaved embodiment of the present invention is nowdescribed. In this embodiment, the check symbols and the GP symbol arecomputed using a generator polynomial g"(X), which is derived fromgenerator polynomial g'(X) above.

g"(X) is defined as follows: ##EQU11## Polynomial g"(X) is obtained, inaccordance with the present invention, by combining the generatorpolynomial:

    (X.sup.3 +1)(X.sup.3 +α)(X.sup.3 +α.sup.2)

with a second generator polynomial (X+α) over all interleaves. Asdiscussed above, a global parity syndrome S_(GP) can be computed fromthe second generator polynomial (X+α). This global parity syndromeS_(GP), as will be demonstrated below, can be used to estimate thecoefficients of the partial syndrome related to (X³ +α³). The expandedexpression for polynomial g"(X) above is valid for the Galois fieldGF(2⁴) defined in Table 1 above. In the above GF(2⁴) Galois field, with4-bit symbols and a three-way interleave, the number of symbols in eachReed-Solomon code word is provided by 3*(2⁴ -1)=45.

As discussed above, g"(X) can be viewed as a product of polynomials G₁(X) and G₂ (X), which are defined as follows: ##EQU12## The presentembodiment generates the global parity symbol GP outside of theReed-Solomon code word. Using G₁ (X) as the generator function for aReed-Solomon error correcting code, the number of check symbols in theresulting error correcting code is 9, thereby leaving a maximum lengthdata field of 36 data symbols, which fit into 18 bytes. Using G₂ (X) toprovide the global parity symbol GP, the check symbols corresponding toboth polynomials G₁ (X) and G₂ (X) can simply be provided in 5 bytes (10check symbols) following the 18 byte data field. In a computer having abyte-oriented memory organization, having the data, check and globalparity symbols fit into an integral number of bytes is an advantageousarrangement because such arrangement minimizes the complexity due tobyte alignment. Of course, a shorter data field can also be used. Forexample, in one embodiment, only 16 bytes are provided in the datafield.

In this embodiment, the global parity syndrome S_(GP) (α) for polynomialG₂ (X) is related to partial syndrome S₃ (α) of polynomial g'(X) by:

    S.sub.GP (α)=S.sub.3 (α)=S.sub.32 α.sup.2 +S.sub.31 α+S.sub.30

where the syndromes S₃₂, S₃₁, and S₃₀ are respectively the syndromesrelating to factor polynomial (X+α³) in each of interleaves 2, 1, and 0.

According to coding theory, in a w-way interleaved Reed-Solomon code,syndromes S_(jw).sbsb.0, S.sub.(j+1)w.sbsb.0, . . . ,S.sub.(j+i)w.sbsb.0 in interleave w₀ (w₀ =0, 1, 2, . . . . w-1) can becomputed respectively from dividing the code word of each interleave byfactor polynomials (X+α^(j)), (X+α^(j+1)), . . . , (X+α^(j+i)). Thesesyndromes are related, in a single error case, by the followingequations:

    S.sub.jw.sbsb.0 =εα.sup.jl.sbsp.w0 ; S.sub.(j+1).sbsb.w0 =εα.sup.(j+1)l.sbsp.w0 ; . . . ; S.sub.(j+i)w.spsb.0 εα.sup.(j+i)l.sbsp.w0

Thus, in this embodiment, the values of S₃₂, S₃₁, and S₃₀ can beestimated from partial syndromes S₂ w.sbsb.0 and S₁ w.sbsb.0, using therelation: where ES_(3w).sbsb.0 is the estimated value of S_(3w).sbsb.0.In fact, ##EQU13## if any two of the quantities S₃₂, S₃₁, and S₃₀ inpartial syndrome S₃ are found, the third quantity can be easily computedalgebraically. Because S_(GP) (α) is related to S₃ (α), by selecting asG₂ (X) a factor of S₃ (X), further confidence in error detection isachieved by verifying the S_(GP) (α) against an estimated ES_(i) (α)which is computed from the ES_(iw).sbsb.0, according to the relation:

    S.sub.GP (α)=ES.sub.3 (α)=ES.sub.31 α.sup.2 +ES.sub.32 α+ES.sub.30

Of course, the global parity syndrome can also be computed asSGP(α^(v)), where v is any integer, S_(GP) (α^(v)) and S₃ (α^(v)) arerelated by:

    S.sub.GP (α.sup.v)=S.sub.32 α.sup.2v +S.sub.31 α.sup.v +S.sub.30

In fact, the same data integrity assurance can be provided by a globalparity symbol GP constructed such that it's syndrome S_(GP) relates toS₃₂, S₃₁, and S₃₀ through α₂, α₁ and α₀, where α_(i) (i=0, 1, 2) is anynon-zero element of the same GF(2⁴):

    S.sub.GP =S.sub.32 α.sub.2 +S.sub.31 α.sub.1 +S.sub.30 α.sub.0

Thus, polynomial g"(X) has a global distance of 5, representing acorrection capability of one error in each interleave and the ability todetect two additional errors, using only ten check symbols. In thisembodiment, since the global parity symbol GP is not included in thecode word, the error correction code corresponding to generatorpolynomial g"(X) can be viewed as a concatenation of a Reed-Solomon codewith 9 check symbols and a global parity symbol.

The error correcting code of the present invention, for example theerror code corresponding to generator polynomial g"(X), maintains thesame global distance as a corresponding Reed-Solomon code, whilerequiring less overhead storage and decoding than the correspondingReed-Solomon code. The error correction code in this embodiment cancorrect a single burst error spanning four symbols (13 bits), and candetect a single burst error spanning six symbols (21 bits).

As discussed above, to achieve a predetermined level of performance, thefull capability of an error correction code need not be implemented. Ofcourse, to achieve a greater error correction capability, the decodingcircuit necessary becomes increasingly complex. Thus, under the presentinvention, one is still free to apply engineering judgment to achievevarying degrees of error correction and detection capabilities, usingcircuits of commensurate complexities. For example, in theimplementation to be described below, a burst limiting circuit limitsthe error correction span to three symbols (9 bits) and the errordetection span to seven symbols (25 bits).⁵

FIG. 1 shows the organization a code unit 100 used in the presentembodiment. Code unit 100 includes a 45 symbol combination of 4-bit dataand check symbols of a three-way interleaved Reed-Solomon code 101, anda 4-bit "global parity symbol" 102. As shown in FIG. 1, three-wayinterleaved Reed-Solomon code 110 includes a data field 101 of 36symbols, and nine check symbols labelled 111-119. In the presentembodiment, only 16 bytes (i.e. 32 data symbols) of data field 101 areused. Code unit 100 can be used in numerous applications, e.g. as an IDblock to identify a sector of a disk drive. In that application, an IDblock is encoded in the format shown in FIG. 1 and written out to thedisk drive. In a data retrieval operation, the ID block is read anddecoded to verify that the intended sector is accessed. The checksymbols in interleaved Reed-Solomon code 110 are computed over the 36data symbols in data field 101. Global parity symbol 102 is appended tothe end of interleaved Reed-Solomon code 101 and is computed over all 454-bit data symbols and check symbols of interleaved Reed-Solomon code101. In this organization of Reed-Solomon code 110, interleave 2 is tothe left of interleave 1, which is in turn left of interleave 0. Notethat the last data symbol in data field 101 is always an interleave 0data symbol.

In the present embodiment, to generate the check symbols in interleavedReed-Solomon code 101, division by g"(X) is implemented as a cascade oftwo divisions: first by polynomial G₁ (X) and then by polynomial G₂ (X).A direct implementation of the division by G₁ (X) can be achieved usinga feedback linear shift register circuit, such as circuit 200 shown inFIG. 2. The operation of such a direct implementation of polynomialdivision can be found, for example, in Chapter 7 of the text"Error-Correcting Codes" referenced above. Circuit 200 receives oneinput data symbol on lead 201 per clock cycle.

In this embodiment, data to be stored, or data retrieved from the massstorage media, are packed in 8-bit bytes. Hence, an efficient checksymbol generator is preferably one which operates from the packed byteswithout incurring the overhead of unpacking the symbols. An example ofsuch a check symbol generator is shown as shift register circuit 300 inFIG. 3. In shift register circuit 300, data to be stored or dataretrieved from the mass storage media are provided two symbols (i.e. 8bits) per system clock period. When all 36 data symbols are receivedinto circuit 300, registers 301-309 contain the check symbols 111-119respectively. The check symbols 111-119 are output two symbols at a timein the next five system clock periods, during which global parity symbol102 continues to be computed. Global parity symbol 102 is output withthe last check symbol 119.

However, since check symbol generation circuit 300 receives two inputsymbols per clock period to generate in shift registers 301-310 the tencheck symbols 111-119 and 102, the content of each of shift registers301-310 after each system clock period must be the same as thecorresponding shift registers of feedback shift register circuit 200(FIG. 2) after two clock periods. The derivation of the logic equationsfor check symbol generator circuit 300 follows from the requirement thatcheck symbol generation circuit 300 after each system clock period is tobe functionally equivalent to feedback shift register circuit 200 aftertwo system clock periods. A derivation of the logic equations for theinput value for each of registers 301-310 is illustrated by Table 2.

Table 2 is a table showing the values f₀, f₁, and r₀ -r₉ in the feedbackoutput terminals 321 and 322, and each of registers 301-310. Table 2contains three rows labelled states 0-2 respectively. In state 0, thecurrent values of check symbols 111-119 and 102 (i.e. r₀ -r₉) are shownheld in registers 301-310. State 1 shows hypothetically, in terms of f₀,f₁, and r₀ -r₉, the values of feedback output terminals 321 and 322, andeach of registers 301-310, after contributions by data symbol d_(h)(i.e. bits I[7:4] of data byte I) to check symbols 111-119 and 102 areincluded. State 2 shows the values of feedback output terminals 321 and322, and each of registers 301-310, after including the contributions tocheck symbols 111-119 and 102 by data symbol d_(l) (i.e. I[3:0] of theinput data byte I). Feedback shift register circuit 300 transitions tostate 2 from state 0 after one system clock period.

Feedback shift register circuit 300 operates in two phases. In the firstphase ("phase 1"), indicated by the "shift" signal on node 333 at logic"zero" and during which the 36 data symbols are shifted into feedbackshift register circuit 300 two symbols at a time, the values of thecheck symbols 111-119 and 102 are computed. In the second phase ("phase2"), indicated by the "shift" signal on node 333 at logic "one", thecheck symbols 111-119 are shifted out of registers 301-309 two symbolsat a time on nodes 331 and 332, while the contributions of check symbols111-119 to check symbol 102 are computed. Finally, simultaneous with theoutput of check symbol 109 at node 331, check symbol 102 is output onnode 332.

Feedback shift register circuit 300 is constructed in accordance withstate 2 of Table 2. As shown in FIG. 3, the two input data symbols d_(h)and d_(l) are provided on nodes 322 and 327. Data symbols d_(h) andd_(l) are summed (i.e. exclusive-ORed) respectively with the outputvalues r₀ and r₁ of registers 301 and 302 to yield feedback values(d_(h) +r₀) and (d_(l) +r₁) on nodes 334 and 335. Prior to arrival ofdata symbols, registers 301-310 are each initialized to zero. In phase1, AND gates 323 and 325 are "enabled", transmitting the values (d_(h)+r₀) and (d_(l) +r₁) on nodes 334 and 335 to constant multipliers336-321 in accordance with the logic operations of state 2 of Table 2.For example, the input terminals of feedback shift register 305 receivea value equal to (d_(h) +r₀)*α¹¹ +r₆, by operation of multiplier 337 andexclusive-OR circuit 343. The input terminals of shift registers 302,303, 306, and 308 are similarly provided with the values specified understate 2 of Table 2. In addition, shift registers 301, 304, 307 receivesvalues r₂, r₅ and r₈ respectively, each value representing a shift oftwo positions (i.e. division by X²). At the same time, the input valuesd_(h) and d_(l) on nodes 322 and 327 are respectively provided, throughmultiplexers 330 and 329, to summers 345 and 346. At summer 345, theinput value d_(h) is exclusive-ORed (i.e. summed) with the value r₉ inshift register 310. The summed value, i.e. d_(h) +r₉, is then multipliedby α at multiplier 347. The result of this multiplication is then summedat summer 346 with input value d_(l). The result of this summing atsummer 346 is then multiplied by α at multiplier 348 to yield a value α²(d_(h) +r₉)+α*d_(l), which is provided as an input value to shiftregister 310, in accordance with state 2 of table 2.

In phase 2, the input values to multipliers 336-341 are zeroed, so thattwo shift register chains are formed. The first chain consists of shiftregisters 301, 303, 305, 307 and 309. The second chain consists of shiftregisters 302, 304, 306 and 308. Thus, at every system clock period, twocheck symbols are shifted out of registers 301 and 302 and provided onnodes 331 and 332 through multiplexers 330 and 329. At the same time,except for the last check symbol 119, the output check symbols 111-118,which are provided on nodes 331 and 332, are fed back to summers 345 and346 for computation of the global parity symbol 102. When the last checksymbol 119 is output 331, the control signal on lead 350 is asserted, sothat the value at the output terminals of multiplier 347 is providedthrough multiplexers 328 and 329 to node 332 as global parity symbol102. In this embodiment, global check symbol 102 results from theexclusive-OR of check symbol 118 and the value in shift register 310,multiplied by α, at the time check symbols 117 and 118 are output atnodes 331 and 332. In a storage application, an error condition mayexist which causes all symbols stored in the storage system to bezeroed. Under that error condition, as will be evident from the syndromecomputation described below, the resulting syndrome coefficients becomeall zeroes, thereby masking the error condition. To avoid this errorcondition, the check symbols 110-119 and 102 can be stored bit-wiseinverted. Upon data retrieval, i.e. during decoding, check symbols111-119 and 102 are bit-wise inverted, prior to syndrome computation.

In feedback shift register circuit 300, multipliers 336-341 eachmultiply a 4-bit output value of either AND gate 323 or AND gate 325 toone of the factors α³, α¹⁰ and α¹¹. Also, multipliers 347 and 348multiple, respectively, the output values of adders 345 and 346 by thefactor α. Multipliers 336-341 can each be constructed out of multiplierswhich multiply a 4-bit data symbol β to one of the constants α, α², andα³. To create the multipliers for multiplying the data symbol β to theconstants α¹⁰ and α¹¹, the following identities in the Galois fieldGF(2⁴) of Table 1 are used:

    α.sup.10 β=(α.sup.2 +α+1)β=α.sup.2 β+αβ+β

    α.sup.11 β=(α.sup.3 +α.sup.2 +α)β=α.sup.3 β+α.sup.2 β+αβ

Accordingly, 4-bit multipliers for multiplying β to α, α², α³, α¹⁰, andα¹¹ can be implemented from the logic equations shown in Table 3. Table3 shows the logic equations which are used to construct each of the bitsin the output value of these 4-bit multipliers over the Galois fieldGF(2⁴) defined above in Table 1, in which the bits β₃ β₂ β₁ β₀ representthe bits at bit positions 3, 2, 1, and 0, with bit 0 at the leastsignificant position.

During a decoding operation, the partial syndromes S₀, S₁, S₂ arecomputed in accordance with the equations for S_(i), i=0, 1, and 2above. FIGS. 4a, 4b and 4c show respectively partial syndrome circuits400, 430 and 460 for computing partial syndromes S₀, S₁, and S₂.Circuits 400, 430 and 460, similar to linear feedback shift registercircuit 300 above, receive the same two data symbols d_(h) and d_(l) persystem clock period on leads 411 and 412, 441 and 442, and 471 and 472respectively. Accordingly, the logic equations for the next coefficientsof partial syndromes S_(i) (i=0, 1, and 2) in partial syndrome circuits400, 430 and 460 are provided in Table 4. Table 4 expresses in terms ofinput values d_(h) and d_(l), and the previous values r_(ij) (i,j=0, 1,and 2), partial syndromes S_(i). In addition, Table 4 also shows thecomputation of S_(GP) as a function of input data symbols d_(h) andd_(l).

Thus, partial syndrome circuit 400 computes the coefficients S₀₂, S₀₁,and S₀₂ of partial syndrome S₀, partial syndrome circuit 430 computesthe coefficients S₁₂, S₁₁, and S₁₀ of partial syndrome S₁, and partialsyndrome circuit 460 computes the coefficients S₂₂, S₂₁, and S₂₀ ofpartial syndrome S₂. When all data symbols are received into partialsyndrome circuits 400, 430 and 460, registers 401-403, 431-433, and461-463 contains the coefficients S₀₀, S₀₁, S₀₂, S₁₀, S₁₁, S₁₂, S₂₀,S₂₁, and S₂₂ respectively. Registers 401-403, 431-433, and 461-463 areinitialized to zero prior to the arrival of any of the 36 data symbolsof Reed-Solomon code 101. When the last check symbol (global paritysymbol 102) is output, the input signals at 413, 443, and 473 arezeroed.

In practice, coding and decoding of data symbols do not occursimultaneously. For example, in a communication application, encoding isperformed only during data transmission and decoding is performed onlyduring data reception. Similarly, in a storage application, encoding isperformed only when data are stored, and decoding is performed onlyduring data retrieval. Thus, registers can be shared between the codingand decoding circuits. In this embodiment, registers 301-309 are alsoused as registers 401-403, 431-433, and 461-463.

Partial syndrome S_(GP) (X) of the global parity check symbol 102 iscomputed using circuit 300. As explained above, to take advantage of theadditional data integrity assurance of the Reed-Solomon code, thecoefficients S₃₀, S₃₁, and S₃₂ are estimated. The estimatedcoefficients, denoted ES₃₀, ES₃₁, and E₃₂ are derived fromS_(2w).sbsb.0, S_(1w).sbsb.0, and S_(0w).sbsb.0, where w₀ =0, 1, and 2.The syndrome S_(GP) of global parity check symbol 102 cannot be verifiedagainst an estimated S_(GP) until check symbols 110-119 are computed.The syndrome S_(GP) is stored in register 310 and provided on node 349as αS_(GP). If no error is encountered, the final estimated partialsyndrome ES_(GP) should equal partial syndrome S_(GP), where ES_(GP) isdefined as:

    ES.sub.GP =ES.sub.32 α.sup.2 +ES.sub.31 α+ES.sub.30

A syndrome S_(GP2) is obtained by summing the estimated ES_(GP) andS_(GP) :

    S.sub.GP2 =α.sup.-1 (S.sub.GP α)+ES.sub.GP

In this embodiment, S_(GP2) is implemented in hardware by the circuitrepresented schematically in FIG. 7. The input values ES_(3w).sbsb.0 (w₀=0, 1, and 2) in FIG. 7 are provided by a circuit 500 illustrated byFIG. 5 discussed below.

As mentioned above, to minimize hardware in one implementation, a burstlimiting circuit, described below, is provided to limit error correctionto within a 9-bit burst, or no more than one symbol error in eachinterleave.

Also, error location 1_(w).sbsb.0 in interleave w₀ is provided by theequation: ##EQU14##

To locate the physical location within the Reed-Solomon code 101, avalue NIBBLE_(w).sbsb.0 is computed in each interleave w₀ from errorlocation 1_(w).sbsb.0 :

    NIBBLE.sub.w.sbsb.0 =9-i-3*1.sub.w.sbsb.0

This value NIBBLE_(w).sbsb.0 specifies the physical location of the dataor check symbol where the error occurred. The value of NIBBLE_(w).sbsb.0indicates the location of the error nibble, as measured from checksymbol 111. For example, if the length of the data field is 16 bytes,and NIBBLE_(w).sbsb.0 has a value of -3, then the error occurs at thelower nibble of byte 15. Tables 5a, 5b and 5c show the physical errorlocations in each of interleaves 0, 1, and 2 respectively. Consequentlyalso, a NIBBLE_(w).sbsb.0 value between 0-8 indicates an error occurringin one of the 5 check bytes in interleaved Reed Solomon code 110. If thenegative value of NIBBLE_(w).sbsb.0 has a magnitude greater than twicethe length of data field 101, then an out of range error has occurred.

FIG. 5 shows schematically a decoder circuit 500 for interleave w₀ inaccordance with the present invention. As shown in FIG. 5, partialsyndromes S_(1w).sbsb.0, S_(2w).sbsb.0, and S_(0w).sbsb.0 are providedas input values to circuit 500. Circuit 500 provides as an output valuea 7-bit output value of NIBBLE_(w).sbsb.0 (NIBBLE[6:0]) on bus 506 theerror pattern S_(0w).sbsb.0 on 4-bit bus 507 the 4-bit error locationES_(3w).sbsb.0, and the expected 4-bit estimated partial syndromes ES₃w₀ are combined three estimated partial syndrome ES_(3w).sbsb.0 on bus509. The (described below) to derive syndrome S_(GP). As mentioned abovewith respect to FIG. 7, when S_(GP) is non-zero, the error pattern isgiven by:

    S.sub.GP2 =ES.sub.32 α.sup.2 +ES.sub.31 α+ES.sub.30 +(S.sub.GP α)α.sup.-1

where `+` denotes an "exclusive or" operation.

The value of NIBBLE_(w).sbsb.0 in the present embodiment is computed bya table look-up in circuit 520 using the value ##EQU15## on bus 521,which is computed in multiplier 522 as the product of the valueS_(2w).sbsb.0 on bus 502, with the output value of inverse circuit 523.Inverse circuit 523 provides as output the multiplicative inverse ofS_(1w).sbsb.0 in the GF(2⁴) Galois field defined in Table 1. Inversecircuit 523 implements a table look-up of multiplicative inverses. Themultiplicative inverses of the elements in the Galois field GF(2⁴) ofTable 1 are shown in Table 7. Multipliers 522 and 524 are 4-bit by 4-bitgeneral purpose multipliers in the Galois field GF(2⁴).

The value ES_(3w).sbsb.0 is computed in multiplier 525 as the product ofthe value ##EQU16## and S_(2w).sbsb.0. In this embodiment, ifS_(0w).sbsb.0, S_(1w).sbsb.0, and S_(2w).sbsb.0 are all zero (asdetermined by comparators 526, 527 and 528), or if S_(0w).sbsb.0*S_(2w).sbsb.0 equals S_(1w).sbsb.0², then it may be concluded thateither no error has occurred, or a correctable error has occurred ininterleave w₀. Any other condition signifies the occurrence of anuncorrectable error. In circuit 500, the value of S_(1w).sbsb.0²computed by squaring multiplier 525. Squaring multiplier 525 implementsthe following equation, for β=[β₃ β₂ β₁ β₀ ], in the Galois field GF(2⁴)defined in Table 1: ##EQU17##

Circuit 500 provides as output signals two error flags SYNOK_(w).sbsb.0and ERR_(w).sbsb.0 for each interleave w₀. SYNOK_(w).sbsb.0, when set,signals either (a) no error, or (b) a correctable error is detected inthe interleave w₀. When reset, SYNOK_(w).sbsb.0 represents occurrence ofan uncorrectable error. These error conditions are summarized in Table6. A global error control signal ERR is provided to indicate that anerror is detected. The error control signal ERR is derived in thepresent embodiment by:

    ERR=ERR.sub.2 ERR.sub.1 ERR.sub.0 (S.sub.GP ≠0)

where denotes an "OR" operation.

In addition, a control signal ERRINGP is set when an error is detectedin the global parity symbol. ERRINGP is derived by:

    ERRINGP=ERR.sub.0 (S.sub.GP2 ≠0)

where denotes an "AND" operation.

The 4-bit error patterns ERRPAT0, ERRPAT1, and ERRPAT2 are provided bythe equations:

    ERRPAT0=S.sub.00 +S.sub.GP2

    ERRPAT1=S.sub.01

    ERRPAT2=S.sub.02

Error patterns ERRPAT0, ERRPAT1 and ERRPAT2 are provided to derive theerror patterns for error correction.

The present embodiment corrects a single burst error spanning no morethan 3 symbols. Within interleaved Reed-Solomon code 101, the firsterror symbol in such a single error burst can occur in any one of thefollowing six situations: (a) in interleave 2, at the lower nibble of abyte, with a 2-byte error pattern ERRPAT given by {0000, ERRPAT2,ERRPAT1, ERRPAT0}; (b) in interleave 2, at the upper nibble of a byte,with a 2-byte error pattern ERRPAT given by {ERRPAT2, ERRPAT1, ERRPAT0,0000}; (c) in interleave 1, at the lower nibble of a byte, with a 2-byteerror pattern ERRPAT given by {0000, ERRPAT1, ERRPAT0, ERRPAT2}; (d) ininterleave 1, at the upper nibble of a byte, with a 2-byte ERRPAT errorpattern given by {ERRPAT1, ERRPAT0, ERRPAT2, 0000}; (e) in interleave 0,at the lower nibble of a byte, with a 2-byte error pattern ERRPAT givenby {0000, ERRPAT0, ERRPAT2, ERRPAT1}; and (f) in interleave 1, at theupper nibble of a byte, with a 2-byte error pattern ERRPAT given by{ERRPAT0, ERRPAT2, ERRPAT1, 0000}. In addition, if a single burst erroris detected in global parity symbol 102, as indicated by error controlsignal ERRINGP, the error is correctable if no error is detected ininterleave 0. In that case, the 2-byte error pattern ERRPAT is given by{0000, ERRPAT2, ERRPAT1, ERRPAT0}y. In view that an error in globalcheck symbol 102 is correctable only if no error occurs in interleave 0,certain portions of the error correction data path can be shared betweenthe error pattern ERRPAT0 in interleave 0 and the global check symbol'serror pattern.

Any error within the burst limit of this embodiment can be corrected bylocating the consecutive two bytes ERRBYTEA and ERRBYTEB at which theerror occurs. To correct ERRBYTEA and ERRBYTEB, ERRBYTEA and ERRBYTEBare exclusive-ORed with the 2-byte error pattern ERRPAT. In thisembodiment, errors other than the correctable errors enumerated aboveare not corrected.

FIG. 6 shows a burst limiter circuit 500 providing a 2-byte errorpattern ERRPAT from the error patterns in each interleave and the errorpattern corresponding to an error in global check symbol 102. As shownin FIG. 6, 4-bit error patterns ERRPATi from interleaves 0-2 and globalerror pattern S_(GP2) are received on 4-bit busses 601-604 into burstlimiter circuit 600. ERRPAT0 is bitwise-ORed with S_(GP2) to be used asan input value to four 4-bit 6:1 multiplexers 610-613. The other inputdata to the 4-bit 6:1 multiplexers 610-613 are ERRPAT1, ERRPAT2, and aconstant value '0000. Multiplexers 610-613 are selected by controlsignals XOXX, 0XXX, X1XX, 1XXX, X2XX, and 2XXX. Control signal Xw₀ XX ,w₀ =0, 1 or 2, represents the condition in which the first error in asingle error burst occurs in interleave w₀ and at the lower nibble of abyte. Control signal w₀ XXX, w₀ =0, 1 or 2, represents the condition inwhich the first error in a single error burst occurs in interleave w₀and at the upper nibble of a byte. Of course, as discussed above, totake advantage that a correctable error in global check symbol 102cannot occur simultaneously with an error in interleave 0 and which isan upper nibble of a byte, control signal 0XXX is also set when theglobal check symbol 102 contains an error.

The above detailed description is provided to illustrate the embodimentsof the present invention, and should not be taken as limiting the scopeof the present invention. Various modifications and variations withinthe scope of the present invention are possible. For example, eventhough the present invention is illustrated by operations in the Galoisfield GF(2⁴), one of ordinary skill would appreciate the principles ofthe present invention are equally applicable to Galois fields of othercardinalities. The present invention is defined by the following claims.

We claim:
 1. A method for providing a w-way interleaved Reed-Solomonerror correcting code word in a data storage or data communicationapplication, comprising the steps of:receiving a plurality of datasymbols; computing, in each interleave a code word including said datasymbols and a plurality of check symbols, said check symbols beinggenerated by a generator polynomial given by:

    G(X)=(X+α.sup.j)(X+α.sup.j+1)(X+α.sup.j+2) . . . (X+α.sup.j+i-1)(X+α.sup.j+i)

where α is a primitive element of GF(2^(m)) and, i and j are integers;providing a global parity symbol GP associated with a syndrome S_(GP)given by one of: ##EQU18## where γ₀, γ₁, . . . γ_(w-1) are non-zeroelements of a galois field GF(2^(m)), and S.sub.(i+j+1)w.sbsb.0 andS.sub.(j-1)w.sbsb.0 are, respectively, the partial syndromescorresponding to (X+α^(i+j+1)) and (X+α^(j-1)) for interleave w₀ ; andfor each interleave, transmitting to a storage device or a transmissionmedium, in accordance with said data storage or data communicationapplication, said code word and said associated global parity symbol GP;wherein said check symbols are generated by a single generatorpolynomial:

    G.sub.w (X)=(X.sup.w +α.sup.j)(X.sup.w +α.sup.j+1) . . . (X.sup.w +α.sup.j+i-1)(X.sup.w +α.sup.j+i).


2. A method as in claim 1, wherein said the number w of interleavesdivides (j+i+1), and said global parity symbol GP being computed overall interleaves using a single second generator function ##EQU19##
 3. Amethod as in claim 1, wherein said number w of interleaves divides(j-1), and said global parity symbol GP being computed over allinterleaves using a single second generator function ##EQU20##
 4. Amethod as in claim 1, wherein said global parity symbol GP is computedas part of said Reed-Solomon error correcting code word, such that anerror in said global parity symbol is detected by a non-zero syndromecomputed from said check symbols and said global parity symbol.
 5. Amethod as in claim 1, wherein said global parity symbols and said checksymbols are generated simultaneously by the generator polynomial:##EQU21##
 6. A method as in claim 1, wherein said global parity symbolsand said check symbols are generated simultaneously by the generatorpolynomial: ##EQU22##
 7. A method as in claim 1, furthercomprising:receiving from said storage device or transmission mediumsaid Reed-Solomon error correcting code word; and decoding said errorcorrection and detecting code by computing partial syndromes S_(j),S_(j+i), S_(j+2), . . . , S_(j+i), of said generator function and saidsyndrome S_(GP) ; wherein said Reed-Solomon error correcting code is3-way interleaved, said method further comprises the step of estimatingsaid syndrome S_(GP) using the relation:

    S.sub.GP =S.sub.3 (α)=S.sub.32 α.sup.2 +S.sub.31 α+S.sub.30.


8. A method as in claim 7, wherein said Reed-Solomon error correctingcode is 3-way interleaved and said global parity symbol GP is generatedby a polynomial (X+α^(v)), where v is an integer, said method furthercomprising the step of estimating said syndrome S_(GP) using therelation:

    S.sub.GP =S.sub.32 α.sup.2v +S.sub.31 α.sup.v +S.sub.30.


9. A method as in claim 7, wherein said Reed-Solomon error correctioncode is 3-way interleaved, further comprising the step of estimatingsaid syndrome S_(GP) using the relation:

    S.sub.GP =S.sub.32 α.sub.2 +S.sub.31 α.sub.1 +S.sub.30 α.sub.0

where α₀, α₁ and α₂ are non-zero elements of said Galois field.